Gate stack engineering and thermal treatment on electrical and interfacial properties of Ti/Pt/HfO 2 /InAs p MOS Capacitors

Effects of gate stack engineering and thermal treatment on electrical and interfacial properties of Ti/Pt/HfO ₂/InAs metal insulator semiconductor (MIS) capacitors were systematically evaluated in terms of transmission electron microscopy, energy dispersive X-ray spectroscopy, current-voltage, and capacitance-voltage characterizations. A 10 nm thick Pt metal effectively suppresses the formation of interfacial oxide, TiO ₂, between the Ti gate and HfO ₂ gate dielectric layer, enhancing the gate modulation on the surface potential of InAs. An in situ HfO ₂ deposition onto the n-InAs channel with an interfacial layer (IL) of one-monolayer InP followed by a 300°C post-metal-anneal produces a high-quality HfO ₂/InAs interface and thus unravels the annoying Fermi-level pinning, which is evidenced by the distinct capacitance dips in the high-/low-frequency C-V characteristics. The interface trap states could be further suppressed by replacing the InP IL by an As-rich InAs, which is substantiated by a gate leakage reduction and a steep voltage-dependent depletion capacitance.