Gate oxide scaling limits and projection

Chen-Ming Hu*

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

101 Scopus citations

Abstract

MOSFET gate oxide scaling limits are examined with respect to time-dependent breakdown, defects, plasma process damage, mobility degradation, poly-gate depletion, inversion layer thickness, tunneling leakage, charge trapping, and gate delay. It is projected that the operating field will stay around 5MV/cm for reliability and optimum speed. Tunneling leakage prevents scaling below 2nm, which is sufficient for MOSFET scaling to 0.05μm.

Original languageEnglish
Pages (from-to)319-322
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1 Dec 1996
EventProceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 8 Dec 199611 Dec 1996

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