Gate-oxide reliability on CMOS analog amplifiers in a 130-nm low-voltage CMOS processes

Jung Sheng Chen*, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

The effect of gate-oxide reliability in MOSFET on common-source amplifiers is investigated with the non-stacked and stacked structures in a 130-nm low-voltage CMOS process. The supply voltage of 2.5 V is applied on the amplifiers to accelerate and observe the impact of gate-oxide reliability on circuit performances including small-signal gain, unity-gain frequency, and output DC voltage level under DC stress and AC stress with DC offset, respectively. The small-signal parameters of amplifier with non-stacked structure strongly degrade under such overstress conditions. The gate-oxide reliability in analog circuit can be improved by stacked structure for small-signal input and output applications.

Original languageEnglish
Title of host publicationProceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006
Pages45-48
Number of pages4
DOIs
StatePublished - 1 Dec 2006
Event13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006 - Singapore, Singapore
Duration: 3 Jul 20067 Jul 2006

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006
CountrySingapore
CitySingapore
Period3/07/067/07/06

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