Effects of plasma induced charging on dielectric integrity in a CMOS technology with n- and p- type polysilicon gates have been studied in detail. We show that p-gates are much more sensitive to charging than n-gates. Charge to breakdown in capacitors with a large p-type polysilicon plate is also reduced by charging damage, in spite of their low antenna ratios. We attribute this sensitivity of p-type gates to the low QBD of p-type gate capacitors for electron injection from the gate. By optimizing the fabrication processes, the amount of charging damage has been reduced to a negligible value, and good quality gate oxide has been achieved. Care must be exercised when interpreting QBD and leakage data on capacitors, to eliminate the effects of process induced charging.
|Number of pages||4|
|State||Published - 1996|
|Event||Proceedings of the 1996 1st International Symposium on Plasma Process-Induced Damage, P2ID - Santa Clara, CA, USA|
Duration: 13 May 1996 → 14 May 1996
|Conference||Proceedings of the 1996 1st International Symposium on Plasma Process-Induced Damage, P2ID|
|City||Santa Clara, CA, USA|
|Period||13/05/96 → 14/05/96|