Gate-induced drain leakage in LDD and fully-overlapped LDD MOSFETs

S. Parke*, J. Moon, P. Nee, J. Huang, Chen-Ming Hu, P. K. Ko

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

6 Scopus citations


It is shown that lightly doped drain (LDD) devices exhibit substantial reductions in gate-induced drain leakage (GIDL) current as compared with the conventional single-drain (SD) device. The fully overlapped LDD structure can exhibit low GIDL approaching that of the nonoverlapped LDD as the n- concentration is increased toward 1 × 1019/cm3. A longer n- spacer also helps reduce GIDL in the fully overlapped devices. These GIDL design constraints must be weighed against the hot-electron reliability and device performance constraints in order to optimize the drain design.

Original languageEnglish
Pages (from-to)49-50
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - 1 Dec 1991
Event1991 Symposium on VLSI Technology - Oiso, Jpn
Duration: 28 May 199130 May 1991

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