Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack

C. H. Cheng*, K. I. Chou, Albert Chin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (Vt) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process.

Original languageEnglish
Pages (from-to)35-38
Number of pages4
JournalMicroelectronic Engineering
Volume109
DOIs
StatePublished - 30 Apr 2013

Keywords

  • Gate first
  • LaO
  • Low EOT
  • TiLaO

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