A new gate current variation (σIg) has been proposed for the first time and demonstrated on the trigate devices. It was found that gate current variation can serve as an indicator of the gate sidewall surface roughness. A new theory has then been developed and verified experimentally on trigate devices with various fin heights. Results show that surface roughness increases with the increasing fin height. In addition, hot carrier and NBT stresses have also been performed for trigate CMOS devices. It was found that NBTI exhibits the worst Ig variation. Finally, this theory has been tested on the SRAM to examine the standby power dissipation. Results show that the power dissipation is dominated by the pFET NBTI effect.