Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels

Chun Jung Su*, Tzu I. Tsai, Yu Ling Liou, Zer Ming Lin, Horng-Chih Lin, Tien-Sheng Chao

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

159 Scopus citations

Abstract

In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.

Original languageEnglish
Article number5716662
Pages (from-to)521-523
Number of pages3
JournalIEEE Electron Device Letters
Volume32
Issue number4
DOIs
StatePublished - 1 Apr 2011

Keywords

  • Accumulation mode
  • gate all around (GAA)
  • inversion mode (IM)
  • nanowire (NW)
  • thin-film transistor (TFT)

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