GaAs power FET with zero-temperature-coefficient

Tsuyoshi Tanaka*, Hidetoshi Furukawa, Daisuke Ueda

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


A GaAs power FET with zero-temperature-coefficient has been developed for the first time. We found drain current (Id) and threshold voltage (Vth) shifts are strongly dependent on the mechanical stress inside a chip which generates piezoelectric charges in the channel. Such stress is originally caused by the difference of the thermal expansion coefficients of GaAs and base-metal. The sign of piezoelectric charge distribution can be controlled by the tensor product of the stress and crystal orientation. Using this inherent feature of GaAs material, we have developed a new temperature compensation technique of GaAs power FET just by choosing a proper gate orientation.

Original languageEnglish
Pages (from-to)557-560
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
StatePublished - 1 Dec 1997
Event1997 International Electron Devices Meeting - Washington, DC, USA
Duration: 7 Dec 199710 Dec 1997

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