GaAs BiFET LSI technology

W. J. Ho*, Mau-Chung Chang, S. M. Beccue, P. J. Zampardi, J. Yu, A. Sailer, R. L. Pierson, K. C. Wang

*Corresponding author for this work

Research output: Contribution to conferencePaper

15 Scopus citations

Abstract

A GaAs BiFET LSI technology has been successfully developed for low power, mixed mode communication circuit applications. The direct placement of the FET on the HBT emitter cap layer simplifies the device epitaxial growth and process integration. High integration levels and functional circuit yield have been achieved. Excellent HBT and FET characteristics have been produced, with the noise figure of the FETs comparable to those of traditional MESFETs, enabling them to perform well in front end receiver applications. Through this technology, several LSI circuits, including 32-bit by 2-bit shift registers and a single-chip DRFM have been successfully demonstrated.

Original languageEnglish
Pages47-50
Number of pages4
StatePublished - 1 Dec 1994
EventProceedingsof the 1994 IEEE GaAs IC Symposium - Philadelphia, PA, USA
Duration: 16 Oct 199419 Oct 1994

Conference

ConferenceProceedingsof the 1994 IEEE GaAs IC Symposium
CityPhiladelphia, PA, USA
Period16/10/9419/10/94

Fingerprint Dive into the research topics of 'GaAs BiFET LSI technology'. Together they form a unique fingerprint.

  • Cite this

    Ho, W. J., Chang, M-C., Beccue, S. M., Zampardi, P. J., Yu, J., Sailer, A., Pierson, R. L., & Wang, K. C. (1994). GaAs BiFET LSI technology. 47-50. Paper presented at Proceedingsof the 1994 IEEE GaAs IC Symposium, Philadelphia, PA, USA, .