Future perspective and scaling down roadmap for RF CMOS

E. Morifuji*, H. S. Momose, T. Ohguro, T. Yoshitomi, H. Kimijima, F. Matsuoka, M. Kinugawa, Y. Katsumata, H. Iwai

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

67 Scopus citations

Abstract

Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on the simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100nm gate length generations.

Original languageEnglish
Pages (from-to)163-164
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1999
EventProceedings of the 1999 Symposium on VLSI Technology - Kyoto, Jpn
Duration: 14 Jun 199916 Jun 1999

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