Future perspective and scaling down roadmap for RF CMOS

E. Morifuji*, H. S. Momose, T. Ohguro, T. Yoshitomi, H. Kimijima, F. Matsuoka, M. Kinogawa, Y. Kalshimata, H. Iwai

*Corresponding author for this work

Research output: Contribution to conferencePaper

39 Scopus citations

Abstract

Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on the simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100nm gate length generations.

Original languageEnglish
Pages165-166
Number of pages2
DOIs
StatePublished - 1999
EventProceedings of the 1999 Symposium on VLSI Circuits - Kyoto, Jpn
Duration: 17 Jun 199919 Jun 1999

Conference

ConferenceProceedings of the 1999 Symposium on VLSI Circuits
CityKyoto, Jpn
Period17/06/9919/06/99

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    Morifuji, E., Momose, H. S., Ohguro, T., Yoshitomi, T., Kimijima, H., Matsuoka, F., Kinogawa, M., Kalshimata, Y., & Iwai, H. (1999). Future perspective and scaling down roadmap for RF CMOS. 165-166. Paper presented at Proceedings of the 1999 Symposium on VLSI Circuits, Kyoto, Jpn, . https://doi.org/10.1109/VLSIC.1999.797271