Future of CMOS technology

Hiroshi Iwai*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In this paper, limitation and its possible causes for the downscaling of CMOS are discussed from many aspects.

Original languageEnglish
Title of host publication2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW
Pages5-8
Number of pages4
StatePublished - 2004
Event2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW - , Taiwan
Duration: 9 Sep 200410 Sep 2004

Publication series

Name2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW

Conference

Conference2004 Semiconductor Manufacturing Technology Workshop Proceedings, SMTW
CountryTaiwan
Period9/09/0410/09/04

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