Fundamental study on reducing on-resistance by introducing strain into silicon vertical power devices

Takeya Inoue, Takuya Hoshii, Takuo Kikuchi, Hidehiko Yabuhara, Kazuyuki Ito, Kuniyuki Kakushima, Hitoshi Wakabayashi, Hiroshi Iwai, Junichi Tonotani, Kazuo Tsutsui

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we examine the feasibility of reducing the on-resistance by introducing strain into the drift layer of Si vertical power devices. The strain effect on the resistance to vertical conduction in the n--Si layer was evaluated using a four-point bending method. The experimental data correspond well with the theoretical values calculated using the piezoresistive coefficient. These results indicate that strain management is a promising method for reducing the on-resistance of Si vertical power devices.

Original languageEnglish
Title of host publication2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages407-409
Number of pages3
ISBN (Electronic)9781538665084
DOIs
StatePublished - Mar 2019
Event2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 - Singapore, Singapore
Duration: 12 Mar 201915 Mar 2019

Publication series

Name2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019

Conference

Conference2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
CountrySingapore
CitySingapore
Period12/03/1915/03/19

Keywords

  • piezoresistive coefficient
  • strain
  • vertical power device

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