Fully CMOS compatible 3D vertical RRAM with self-Aligned self-selective cell enabling sub-5nm scaling

Xiaoxin Xu, Qing Luo, Tiancheng Gong, Hangbing Lv, Shibing Long, Qi Liu, Steve S. Chung, Jing Li, Ming Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations

Abstract

In low cost vertical resistive switching memory (VRRAM), the inter-layer leakage becomes a serious problem, primarily resulting from the ultimate scaling in the vertical dimension. In this work, for the first time, we present a novel approach of fabricating 3D VRRAM using self-Aligned self-selective RRAM to effectively address such challenge. By successfully suppressing the inter-layer leakage, the scaling limit of VRRAM could be extended beyond 5 nm. Other benefits, such as high nonlinearity (>103), low power consumption (sub-μA), robust endurance and excellent disturbance immunity, were also demonstrated.

Original languageEnglish
Title of host publication2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509006373
DOIs
StatePublished - 21 Sep 2016
Event36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, United States
Duration: 13 Jun 201616 Jun 2016

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2016-September
ISSN (Print)0743-1562

Conference

Conference36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
CountryUnited States
CityHonolulu
Period13/06/1616/06/16

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