Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead

Wen Quan He, Yu Chun Lin, Jui Yi Hung, Shyh-Jye Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper proposes a novel full-digital architecture of adaptive decision feedback equalizer (ADFE) for wireline 2-level pulse amplitude modulation (2-PAM) systems. It is well known that the feedback loop in DFE limits the greatest achievable speed. The proposed scheme begins by deriving coefficient-lookahead concept based on a reasonable assumption, whereupon a preliminary architecture can be implemented using the formula derived. Furthermore, according to channel characteristics, the formula derived can be simplified to break the feedback loop. Finally, the architecture can be easily pipelined and processed in parallel to achieve high throughput rate. Thus, the proposed design is a high speed design with parallel and pipeline architecture. This paper used a TSMC 40 nm CMOS process to fabricate the proposed design with a build-in self-test (BIST) circuit. The measured results show that the throughput rate is up to 16 Gbps.

Original languageEnglish
Title of host publicationProceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
EditorsJunyan Ren, Ting-Ao Tang, Fan Ye, Huihua Yu
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479984831
DOIs
StatePublished - 21 Jul 2016
Event11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
Duration: 3 Nov 20156 Nov 2015

Publication series

NameProceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

Conference

Conference11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
CountryChina
CityChengdu
Period3/11/156/11/15

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