Full-custom all-digital phase locked loop for clock generation

Mu Lee Huang, Chung-Chih Hung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A novel approach of constructing an All-Digital Phase Locked Loop (ADPLL) is presented in this paper. A 3-Step symmetric Time-to-Digital Converter (TDC) is proposed with both long dynamic range and high resolution. The Upper-and-Lower-boundaries-Cut-off-Determination (ULCD) logic is presented for a full-custom digital loop filter. With this method, an all-digital PLL can be designed without synthesis procedures. The Digitally-Controlled Oscillator is designed by ring architecture with periodic variation linear. The dynamic range of the TDC is 7.7 ns and the finest resolution of the TDC is only 12.7 ps. System locked time is only 1.62 us. The rms jitter and P-P jitter is 4.68 ps and 38.68 ps in the measurement results. And the power dissipation is only 7.55 mW.

Original languageEnglish
Title of host publication2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479962754
DOIs
StatePublished - 28 May 2015
Event2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan
Duration: 27 Apr 201529 Apr 2015

Publication series

Name2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
CountryTaiwan
CityHsinchu
Period27/04/1529/04/15

Keywords

  • All-digital PLL
  • Digital Loop Filter
  • Time-to-Digital Converter

Fingerprint Dive into the research topics of 'Full-custom all-digital phase locked loop for clock generation'. Together they form a unique fingerprint.

  • Cite this

    Huang, M. L., & Hung, C-C. (2015). Full-custom all-digital phase locked loop for clock generation. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 [7114567] (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2015.7114567