Full current-mode techniques for high-speed CMOS SRAMs

S. M. Wang*, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference article

4 Scopus citations

Abstract

This paper describes an experimental 32K×8 CMOS SRAM with a 9ns access time at a supply voltage of 3V using a 0.35um 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28mA at 100MHz under typical conditions.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
DOIs
StatePublished - 1 Jan 2002
Event2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
Duration: 26 May 200229 May 2002

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