Full chip power benefits with negative capacitance FETs

Sandeep K. Samal, Sourabh Khandelwal, Asif I. Khan, Sayeef Salahuddin, Chen-Ming Hu, Sung Kyu Lim

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.

Original languageEnglish
Title of host publicationISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509060238
DOIs
StatePublished - 11 Aug 2017
Event22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan
Duration: 24 Jul 201726 Jul 2017

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

Conference22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
CountryTaiwan
CityTaipei
Period24/07/1726/07/17

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