FSM-based formal compliance verification of interface protocols

Che Hua Shih*, Y. A.Ching Yang, Chia Chih Yen, Juinn-Dar Huang, Jing Yang Jou

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

Verifying whether a building block conforms to a specific interface protocol is one of the important steps in a platform-based system-on-a-chip design methodology. There are limitations for most of the existing methods for interface protocol compliance verification. Simulation-based methods have the false positive problem while formal property checking methods may suffer from memory explosion and excessive runtime. In this paper, we propose a novel approach for interface protocol compliance verification. The properties of the interface protocol are first specified as a specification FSM. Then the compliance of interface logic is formally verified at the higher FSM level so that the required memory and runtime can be greatly reduced. Finally, it is shown theoretically and experimentally that the proposed algorithm possesses acceptably low time complexity for practical applications.

Original languageEnglish
Pages (from-to)1601-1617
Number of pages17
JournalJournal of Information Science and Engineering
Volume26
Issue number5
DOIs
StatePublished - 1 Sep 2010

Keywords

  • Formal verification
  • Functional verification
  • Interface compliance verification
  • Platform-based design methodology
  • Protocol modeling

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