Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition

Chun Chieh Huang*, Shao Hang Hung, Jen Feng Chung, Lan-Da Van, Chin Teng Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

We proposed a novel analog circuit design which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). It has not only reduced the number of outer components, and enhances a better signal-to-noise ratio (SNR). The chip includes a current-balancing instrumentation amplifier, switched-capacitor filter, non-overlapping clock generator, and a programmable gain amplifier (PGA). It was fabricated by TSMC 0.35 μm CMOS 2P4M standard process, with CMRR 155 dB CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 μW under ±1.5V supply.

Original languageEnglish
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages2717-2720
Number of pages4
DOIs
StatePublished - 19 Sep 2008
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: 18 May 200821 May 2008

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period18/05/0821/05/08

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