@inproceedings{5f4d717ab9e34cdc8bf6f67d192a50cb,
title = "FPGA implementation of OFDM baseband processor",
abstract = "This paper explains how to use a field programmable gate array (FPGA) evaluation board, which has limited resources, to build a reduced version of the OFDM baseband processor platform. The contribution in this paper is to propose conversion approaches and establish that these efficient approaches can be used to translate the design of the silicon OFDM-baseband processor into the design of a FPGA. The innovation in this paper is in providing a simple and effective way to accomplish a pipelined divider on an FPGA.",
keywords = "CE: Clock Enable, IP: Intellectual Property OFDM: Orthogonal Frequency-Division Multiplexing, LUT: Look-Up Table, MIMO: Multpile-Input and Multiple-Output, MMCM: Mixed-Mode Clock Manager, OR1200: OpenRISC 1200, RALU: Reconfigurable Arithmatic Logic Unit",
author = "Kuohua Sung and Terng-Yin Hsu",
year = "2017",
month = oct,
day = "18",
doi = "10.1109/DESEC.2017.8073864",
language = "English",
series = "2017 IEEE Conference on Dependable and Secure Computing",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "466--467",
booktitle = "2017 IEEE Conference on Dependable and Secure Computing",
address = "United States",
note = "null ; Conference date: 07-08-2017 Through 10-08-2017",
}