FPGA implementation of OFDM baseband processor

Kuohua Sung, Terng-Yin Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


This paper explains how to use a field programmable gate array (FPGA) evaluation board, which has limited resources, to build a reduced version of the OFDM baseband processor platform. The contribution in this paper is to propose conversion approaches and establish that these efficient approaches can be used to translate the design of the silicon OFDM-baseband processor into the design of a FPGA. The innovation in this paper is in providing a simple and effective way to accomplish a pipelined divider on an FPGA.

Original languageEnglish
Title of host publication2017 IEEE Conference on Dependable and Secure Computing
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781509055692
StatePublished - 18 Oct 2017
Event2017 IEEE Conference on Dependable and Secure Computing - Taipei, Taiwan
Duration: 7 Aug 201710 Aug 2017

Publication series

Name2017 IEEE Conference on Dependable and Secure Computing


Conference2017 IEEE Conference on Dependable and Secure Computing


  • CE: Clock Enable
  • IP: Intellectual Property OFDM: Orthogonal Frequency-Division Multiplexing
  • LUT: Look-Up Table
  • MIMO: Multpile-Input and Multiple-Output
  • MMCM: Mixed-Mode Clock Manager
  • OR1200: OpenRISC 1200
  • RALU: Reconfigurable Arithmatic Logic Unit

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