Ion implantation through metal (ITM) or metal silicide (ITS) appears to be an attractive technique for self-aligned silicided shallow junction formation. Since most of the implanted ions are confined in the barrier film, the damage generated in the silicon substrate is reduced and so is the required post-implant annealing temperature. The purpose of this work is to study the capability of using Pt and PtSi in the ITM/ITS technique. As+ ions were implanted through 30-nm Pt or 60-nm PtSi at 80 keV with doses ranging from 1×1015 to 1×1016 cm-2. The implanted samples were annealed from 650 to 800 °C. Junction depths measured by spreading resistance and secondary-ion mass spectroscopy on 750 °C annealed samples are about 0.11 and 0.13 μm for the ITS and ITM schemes, respectively. The reverse area and peripheral leakage current density (J RA and JRP) are separated by measuring diodes of different size. All samples with a dose of 1×1015 cm-2 failed due to an insufficient amount of dopants which were incorporated into Si. For a dosage greater than 5×1015 cm-2, the JRA at -5 V is less than 0.2 nA/cm2 and the forward ideality factor is lower than 1.02 for the ITS samples annealed at 750 °C. Activation energy measurement shows that the JRA is diffusion-component dominated while the JRP is generation-component dominated at room temperature. Surface generation current and lateral implantation damage-induced current are examined and discussed in detail. A possible reason is that the lateral junction depth is less than the vertical junction depth and the depletion region may be extended to near the PtSi/Si interface. Annealing at 800 °C degrades the junction characteristics because the Pt from PtSi diffuses into the junction region. Based on the experimental results and analysis we conclude that either Pt or PtSi film can be employed as an efficient barrier film in the ITM/ITS technique. A high-quality and ultrashallow junction can be fabricated using furnace annealing at temperature as low as 750 °C. The peripheral current generated at the silicide/silicon interface dominates the reverse junction current and cannot be avoided for the silicided junction with a junction depth less than 50 nm from the interface. This factor acts as a physical limitation as the junction depth scales down.