Formal compliance verification of interface protocols

Ya Ching Yang*, Juinn-Dar Huang, Chia Chih Yen, Che Hua Shih, Jing Yang Jou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Verifying whether a building block conforms to certain interface protocol is one of the important steps while constructing an SoC. However, most existing methods have their own limitations. Simulation-based methods have the false positive problem while formal property checking methods may suffer from memory explosion and excessive runtime. In this paper, we propose a novel branch-and-bound algorithm for interface protocol compliance verification. The properties of the interface protocol are specified as a specification FSM, and the interface logic is formally verified at the higher FSM level. Using the FSM for property specification is relatively systematic than using other proprietary property languages, which greatly reduces the possibility of incomplete property identification. And it is shown theoretically and experimentally that the proposed algorithm can finish in reasonable time complexity.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages12-15
Number of pages4
DOIs
StatePublished - 1 Dec 2005
Event2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
Duration: 27 Apr 200529 Apr 2005

Publication series

Name2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Volume2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
CountryTaiwan
CityHsinchu
Period27/04/0529/04/05

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  • Cite this

    Yang, Y. C., Huang, J-D., Yen, C. C., Shih, C. H., & Jou, J. Y. (2005). Formal compliance verification of interface protocols. In 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) (pp. 12-15). [1500007] (2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT); Vol. 2005). https://doi.org/10.1109/VDAT.2005.1500007