A folded-channel transistor structure improves the short-channel effect immunity of deep-sub-tenth micron MOSFETs with gate length down to 20 nm. In the structure, a transistor is formed in a vertical ultrathin Si fin and is controlled by a double gate which suppresses short-channel effects. The two gates are self-aligned and aligned to the S/D. The S/D is raised to reduce parasitic resistance. New low-temperature gate or ultrathin gate dielectric materials can be used because they are deposited after the S/D. Finally, the structure is quasi-planar because the Si fins are relatively short.
|Number of pages||3|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 1998|
|Event||Proceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA|
Duration: 6 Dec 1998 → 9 Dec 1998