Folded-channel MOSFET for deep-sub-tenth micron era

Digh Hisamoto*, Wen Chin Lee, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Kazuya Asano, Tsu Jae King, Jeffrey Bokor, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

239 Scopus citations

Abstract

A folded-channel transistor structure improves the short-channel effect immunity of deep-sub-tenth micron MOSFETs with gate length down to 20 nm. In the structure, a transistor is formed in a vertical ultrathin Si fin and is controlled by a double gate which suppresses short-channel effects. The two gates are self-aligned and aligned to the S/D. The S/D is raised to reduce parasitic resistance. New low-temperature gate or ultrathin gate dielectric materials can be used because they are deposited after the S/D. Finally, the structure is quasi-planar because the Si fins are relatively short.

Original languageEnglish
Pages (from-to)1032-1034
Number of pages3
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1 Dec 1998
EventProceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 6 Dec 19989 Dec 1998

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