Fluorinated HfO 2 gate dielectrics engineering for CMOS by pre-and post-CF 4 plasma passivation

Woei Cherng Wu, Chao Sung Lai*, Shih Ching Lee, Ma Ming-Wen, Tien-Sheng Chao, Jer Chyi Wang, Chih Wei Hsu, Pai Chi Chou, Jian Hao Chen, Kuo Hsing Kao, Wen Cheng Lo, Tsung Yi Lu, Li Lin Tay, Nelson Rowell

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

In this paper, we demonstrate TaN/Fluorinated HfO 2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO 2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively. A physical model of shallow and deep trapping level affected by fluorine was proposed to explain the NBTI and PBTI improvements.

Original languageEnglish
Title of host publication2008 IEEE International Electron Devices Meeting, IEDM 2008
DOIs
StatePublished - 1 Dec 2008
Event2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States
Duration: 15 Dec 200817 Dec 2008

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2008 IEEE International Electron Devices Meeting, IEDM 2008
CountryUnited States
CitySan Francisco, CA
Period15/12/0817/12/08

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