Hans P. Zappe*, Rajesh K. Gupta, Kyle W. Terrill, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

6 Scopus citations


The operation of CMOS devices in an electrically floating well is considered. The impetus for this study is the potential reduction of silicon area and wiring complexity attainable when the need for well contacts is eliminated. Experimental p-channel transistor characteristics are presented, for both the floating- and non-floating- well cases. FET device characteristics, namely, subthreshold behavior, junction leakage, and breakdown voltage, are considered. Results indicate that transistor operation is not significantly affected when the well is electrically floated. Latchup hardness is somewhat but not excessively degraded when the well is floated, a result that is explained by means of a simple holding voltage model. It is shown that increased source (emitter) resistance may offset this degradation.

Original languageEnglish
Pages (from-to)517-520
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 1 Dec 1985

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