The operation of CMOS devices in an electrically floating well is considered. The impetus for this study is the potential reduction of silicon area and wiring complexity attainable when the need for well contacts is eliminated. Experimental p-channel transistor characteristics are presented, for both the floating- and non-floating- well cases. FET device characteristics, namely, subthreshold behavior, junction leakage, and breakdown voltage, are considered. Results indicate that transistor operation is not significantly affected when the well is electrically floated. Latchup hardness is somewhat but not excessively degraded when the well is floated, a result that is explained by means of a simple holding voltage model. It is shown that increased source (emitter) resistance may offset this degradation.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 1985|