A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.
|Number of pages||5|
|State||Published - 1 Jan 2000|
|Event||2000 International Conference on Computer Design - Austin, TX, USA|
Duration: 17 Sep 2000 → 20 Sep 2000
|Conference||2000 International Conference on Computer Design|
|City||Austin, TX, USA|
|Period||17/09/00 → 20/09/00|