Fixed-width multiplier for DSP application

Shyh-Jye Jou*, Hui Hsuan Wang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

33 Scopus citations

Abstract

A new compensation method that reduce the error of fixed-width multiplier for digital signal processing (DSP) application is proposed. The designs of using this input-number based compensation method are carried out on array multiplier and Booth multiplier. The hardware complexity is reduced to about 50% of the original multiplier. Design results show that the new architectures have lower hardware overhead, lower error and fast operation speed as compared with other proposed architectures.

Original languageEnglish
Pages318-322
Number of pages5
DOIs
StatePublished - 1 Jan 2000
Event2000 International Conference on Computer Design - Austin, TX, USA
Duration: 17 Sep 200020 Sep 2000

Conference

Conference2000 International Conference on Computer Design
CityAustin, TX, USA
Period17/09/0020/09/00

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