First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate

Chao Ching Cheng, Yun Yan Chung, Uing Yang Li, Chao Ting Lin, Chi Feng Li, Jyun Hong Chen, Tung Yen Lai, Kai Shin Li, Jia Min Shieh, Sheng Kai Su, Hung Li Chiang, Tzu Chiang Chen, Lain Jong Li, H. S.Philip Wong, Chao-Hsin Chien*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS2 p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of 106, a S.S. of 97 mV/dec., and nearly zero DIBL.

Original languageEnglish
Title of host publication2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesT244-T245
Number of pages2
ISBN (Electronic)9784863487178
DOIs
StatePublished - Jun 2019
Event39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan
Duration: 9 Jun 201914 Jun 2019

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2019-June
ISSN (Print)0743-1562

Conference

Conference39th Symposium on VLSI Technology, VLSI Technology 2019
CountryJapan
CityKyoto
Period9/06/1914/06/19

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