Finite state machine synthesis for at-speed oscillation testability

Katherine Shu Min Li*, Chung Len Lee, Tagin Jiang, Chau-Chin Su, Jwu E. Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing, which makes delay-inducing defects detectable. (2) The ATPG is much easier, and the test set is usually smaller. (3) There is no need to store output responses, which greatly reduces the communication bandwidth between the Automatic Test Equipment (ATE) and Circuit under Test (CUT). We provide a register design that supports the oscillation test, and give an effective algorithm for oscillation test generation. Experimental results on MCNC benchmarks show that the proposed test method achieves high fault coverage with smaller number of test vectors.

Original languageEnglish
Title of host publicationProceedings - 14th Asian Test Symposium, ATS 2005
Pages360-365
Number of pages6
DOIs
StatePublished - 1 Dec 2005
Event14th Asian Test Symposium, ATS 2005 - Calcutta, India
Duration: 18 Dec 200521 Dec 2005

Publication series

NameProceedings of the Asian Test Symposium
Volume2005
ISSN (Print)1081-7735

Conference

Conference14th Asian Test Symposium, ATS 2005
CountryIndia
CityCalcutta
Period18/12/0521/12/05

Fingerprint Dive into the research topics of 'Finite state machine synthesis for at-speed oscillation testability'. Together they form a unique fingerprint.

Cite this