Film-profile-engineered IGZO thin-film transistors with gate/drain offset for high voltage operation

Ming Hung Wu, Horng-Chih Lin, Pei-Wen Li, Tiao Yuan Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

IGZO transistors with various gate/drain-offset lengths (Lgdo) were fabricated with the film-profile-engineering method. Breakdown voltage (VBD) of the fabricated devices increases while transconductance (gm) decreases with increasing Lgdo. In contrast, threshold voltage and subthreshold swing remain relatively unchanged. Vbd of ∼80 V is obtained with Lgdo of 0.3 μm. Output characteristics with operation voltage up to 50 V are also demonstrated, evidencing the capability of the device for high-voltage operation. Impact of hot-carrier stress is also investigated in this work.

Original languageEnglish
Title of host publicationProceedings of the 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages272-275
Number of pages4
ISBN (Electronic)9781467382588
DOIs
StatePublished - 9 Sep 2016
Event23rd IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2016 - Singapore, Singapore
Duration: 18 Jul 201621 Jul 2016

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2016-September

Conference

Conference23rd IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2016
CountrySingapore
CitySingapore
Period18/07/1621/07/16

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