Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit

Yuh Kuang Tseng*, Kuo Hsing Cheng, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

This paper describes a new feedback-controlled enhanced-pull-down BiCMOS (FC-EPD-BiCMOS) logic scheme for the low-supply-voltage operation. Through the use of the feedback-controlled enhanced-pull-down structure, the driving capability is improved and bipolar transistor saturation during operation period is avoided. Based upon the proposed structure, both static and differential logic gates are developed. The new BiCMOS three-input NAND gate offers 35% reduction in the propagation delay time as compared to conventional BiCMOS circuits at 2.5 V supply voltage. The proposed three-input FC-EPD-BiCMOS CPL XOR/XNOR gate has 33% improvement in delay time as compared to conventional BiCMOS 3-input XOR/XNOR gates at 2.4 V supply voltage.

Original languageEnglish
Pages (from-to)23-26
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
DOIs
StatePublished - 1 Dec 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: 30 May 19942 Jun 1994

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