Fault models for embedded-DRAM macros

Chia-Tso Chao, Hao Yu Yang, Rei Fu Huang, Shih Chin Lin, G. Yu Chin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first start from an standard SRAM test algorithm and discuss the faults which are not covered in the SRAM testing but should be considered in the DRAM testing. Then we study the behavior of those faults and the tests which can detect them. Also, we discuss how likely each modeled fault may occur on eDRAMs and commodity DRAMs, respectively.

Original languageEnglish
Title of host publication2009 46th ACM/IEEE Design Automation Conference, DAC 2009
Pages714-719
Number of pages6
DOIs
StatePublished - 10 Nov 2009
Event2009 46th ACM/IEEE Design Automation Conference, DAC 2009 - San Francisco, CA, United States
Duration: 26 Jul 200931 Jul 2009

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference2009 46th ACM/IEEE Design Automation Conference, DAC 2009
CountryUnited States
CitySan Francisco, CA
Period26/07/0931/07/09

Keywords

  • Embedded DRAM
  • Memory testing

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  • Cite this

    Chao, C-T., Yang, H. Y., Huang, R. F., Lin, S. C., & Chin, G. Y. (2009). Fault models for embedded-DRAM macros. In 2009 46th ACM/IEEE Design Automation Conference, DAC 2009 (pp. 714-719). [5227104] (Proceedings - Design Automation Conference). https://doi.org/10.1145/1629911.1630097