Fault diagnosis in VLSI/WSI processor arrays.

Sy Yen Kuo*, Kuo-Chen Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An efficient and application-independent fault diagnosis method in VLSI/WSI processor arrays is presented. Four selectors, two comparators, two registers, one latch, and one OR gate are added to each processing element (PE) in the array to make the array easily diagnosible. By applying functional test patterns to each PE in the array, multiple-PE failures can be detected and located. In the method, all the PEs perform self-comparison operations simultaneously. The self-comparison approach is applicable to any structure of PEs. The test pattern size is fixed regardless of the array size. Although the whole design is for a unidirectional two-dimensional processor array, the same methodology can be extended to other kinds of array structures. This approach is unique in the multiple fault diagnosis capability as well as high-fault coverage and small testing time. Switch and link faults as well as PE faults are included in the fault model.

Original languageEnglish
Title of host publicationProc Int Conf Wafer Scale Integr
EditorsEarl Swartzlander, Joe Brewer
PublisherPubl by IEEE
Pages325-333
Number of pages9
ISBN (Print)0818699019
DOIs
StatePublished - 1 Dec 1989
EventProceedings: International Conference on Wafer Scale Integration - San Francisco, CA, USA
Duration: 3 Jan 19895 Jan 1989

Publication series

NameProc Int Conf Wafer Scale Integr

Conference

ConferenceProceedings: International Conference on Wafer Scale Integration
CitySan Francisco, CA, USA
Period3/01/895/01/89

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