Fault coverage estimation model for partially testable multichip modules

W. D. Tseng*, Kuo-Chen Wang

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

This paper proposes a simple and efficient model for designers to estimate fault coverage for partially testable MCMs. This model relates fault coverage, test methodology, and the ratio and distribution of DFT dies (dies with design for testability features) in an MCM. Experimental results show that our model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. In addition, the upper bound for fault coverage is also analyzed to guide the designers to know when to stop the effort in planning the use of DFT dies. Two defect level estimation models which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and non-equiprobable faults, respectively, are also presented and evaluated.

Original languageEnglish
Pages72-77
Number of pages6
DOIs
StatePublished - 1 Dec 1997
EventProceedings of the 1997 Pacific Rim International Symposium on Fault-Tolerant Systems, PRFTS - Taipei, Taiwan
Duration: 15 Dec 199716 Dec 1997

Conference

ConferenceProceedings of the 1997 Pacific Rim International Symposium on Fault-Tolerant Systems, PRFTS
CityTaipei, Taiwan
Period15/12/9716/12/97

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  • Cite this

    Tseng, W. D., & Wang, K-C. (1997). Fault coverage estimation model for partially testable multichip modules. 72-77. Paper presented at Proceedings of the 1997 Pacific Rim International Symposium on Fault-Tolerant Systems, PRFTS, Taipei, Taiwan, . https://doi.org/10.1109/PRFTS.1997.640128