Fault coverage and defect level estimation models for partially testable MCMs

W. D. Tseng*, Kuo-Chen Wang

*Corresponding author for this work

Research output: Contribution to journalArticle


The authors propose a simple and efficient mathematical model for designers to estimate fault coverage for partially testable multichip modules (MCMs). This model shows a relation between fault coverage, test methodology, and the fraction and distribution of design for testability (DFT) dies in MCMs. Experimental results show that the proposed model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. An automatic DFT dies deployment algorithm, based on the genetic algorithm and the model is proposed to help designers to obtain a fault coverage as close to the upper bound of fault coverage as possible. Two defect level estimation models, which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and non-equiprobable faults, respectively, are also formulated and analysed to support the effectiveness of the model.

Original languageEnglish
Pages (from-to)119-124
Number of pages6
JournalIEE Proceedings: Circuits, Devices and Systems
Issue number2
StatePublished - 1 Jan 2000

Fingerprint Dive into the research topics of 'Fault coverage and defect level estimation models for partially testable MCMs'. Together they form a unique fingerprint.

  • Cite this