Fast WAT test structure for measuring VT variance based on latch-based comparators

Kao Chi Lee, Kai-Chiang Wu, Chih Ying Tsai, Chia-Tso Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

As the technology of IC manufacturing continually scales down, process variations become more and more crucial than before. To statistically characterize local process variations, the traditional array-based test structure measures threshold voltage (Vt) for a sufficiently large number of devices-undertest (DUTs). However, the array-based test structure requires long time for DUT-by-DUT measurement; furthermore, it suffers from significant IR drop or leakage current due to the large number of DUTs, which results in the loss of measurement accuracy. In this paper, we present a novel sense-Amplifierbased test structure that can monitor process variations based on rapid characterization of Vt variance, with marginal error of accuracy. A test-chip containing 120 NMOS and 120 PMOS DUTs has been implemented in 28nm CMOS process technology. Various experiments reveal promising efficiency and accuracy of the proposed test structure, for characterizing Vt variance.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE 35th VLSI Test Symposium, VTS 2017
PublisherIEEE Computer Society
ISBN (Electronic)9781509044825
DOIs
StatePublished - 15 May 2017
Event35th IEEE VLSI Test Symposium, VTS 2017 - Las Vegas, United States
Duration: 9 Apr 201712 Apr 2017

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference35th IEEE VLSI Test Symposium, VTS 2017
CountryUnited States
CityLas Vegas
Period9/04/1712/04/17

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