Fast transient low-dropout voltage regulator with hybrid dynamic biasing technique for SoC application

Chia Min Chen, Tung Wei Tsai, Chung-Chih Hung

Research output: Contribution to journalArticle

21 Scopus citations

Abstract

This brief presents a low-dropout (LDO) voltage regulator without output capacitors that achieves fast transient responses by hybrid dynamic biasing. The hybrid dynamic biasing in the proposed transient improvement circuit is activated through capacitive coupling. The proposed circuit senses the LDO regulator output change so as to increase the bias current instantly. The proposed circuit was applied to an LDO regulator without output capacitors implemented in standard 0.35-μ m CMOS technology. The device consumes only 25 μ A of quiescent current with a dropout voltage of 180 mV. The proposed circuit reduces the output voltage spike of the LDO regulator to 80 mV when the output current is changed from 0 to 100 mA. The output voltage spike is reduced to 20 mV when the supply voltage varies between 1.3 and 2.3 V with a load current of 100 mA.

Original languageEnglish
Article number6327694
Pages (from-to)1742-1747
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number9
DOIs
StatePublished - 1 Jan 2013

Keywords

  • Capacitive coupling
  • hybrid dynamic biasing
  • low-dropout regulator
  • transient response
  • voltage spike

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