Fast Principal Component Analysis Based on Hardware Architecture of Generalized Hebbian Algorithm

Shiow-Jyu Lin, Yi-Tsan Hung, Wen Jyi Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents a novel hardware architecture for fast principle component analysis (PCA). The architecture is developed based on generalized Hebbian algorithm (GHA). In the architecture, the updating of different synaptic weight vectors are divided into a number of stages. The results of precedent stages are used for the computation of subsequent stages for expediting training speed and lowering the area cost. The proposed architecture has been embedded in a system-on-programmable-chip (SOPC) platform for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for fast PCA in attaining both high performance and low computation time.
Original languageAmerican English
Title of host publicationFast Principal Component Analysis Based on Hardware Architecture of Generalized Hebbian Algorithm
Place of PublicationWuhan, China
PublisherSpringer Berlin Heidelberg
Pages505 - 515
Number of pages11
Volume6382
ISBN (Electronic)978-3-642-16493-4
ISBN (Print)978-3-642-16492-7
StatePublished - 21 Oct 2010

Keywords

  • Principal component analysis (pca)
  • Synaptic Weight
  • Hardware Architecture
  • Direct Memory Access
  • Training Vector

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