Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications

Duo Sheng*, Ching Che Chung, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90° phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3° at 400MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with power-down mode. The proposed DCPS provides the suitable phase shift of control signals for DDR interface where precise control is the key to reliable high-performance operation. Besides, the cell-based implementation makes it easy to target a variety of technologies as a soft silicon intellectual property (IP).

Original languageEnglish
Pages (from-to)634-639
Number of pages6
JournalIEICE Electronics Express
Volume7
Issue number9
DOIs
StatePublished - 10 May 2010

Keywords

  • ADDLL
  • DCPS
  • DDR controller
  • Fast lock
  • Portable

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