Fast intra prediction algorithm and design for high efficiency video coding

Han Chiou Fang, Hung Cheng Chen, Tian-Sheuan Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

To meet the real time demand of HEVC intra encoding, this paper proposed a fast intra prediction algorithm and its design with a gradient weight controlled block size selection to reduce number of PU (prediction unit) sizes to two. These two PU sizes will be further selectively reduced to one based on its SATD distribution. The simulation results show that the proposed algorithm can save 79% encoding time for all-intra main case compared to HM-9.0rc1, with 3.4% BD-rate increase. The hardware design costs 224K gate count and 1.7KB SRAM for 4Kx2k@30fps processing with TSMC 90 nm CMOS technology when operated at 270 MHz operating frequency.

Original languageEnglish
Title of host publicationISCAS 2016 - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1770-1773
Number of pages4
ISBN (Electronic)9781479953400
DOIs
StatePublished - 29 Jul 2016
Event2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
Duration: 22 May 201625 May 2016

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2016-July
ISSN (Print)0271-4310

Conference

Conference2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
CountryCanada
CityMontreal
Period22/05/1625/05/16

Keywords

  • HEVC
  • hardware design
  • intra prediction

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