Failure of on-chip power-rail ESD clamp circuits during system-level ESD test

Cheng Cheng Yen*, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

Four different on-chip power-rail electrostatic discharge (ESD) protection circuits, (1) with typical RC-triggered; (2) with NMOS+PMOS feedback; (3) with PMOS feedback; and (4) with cascaded PMOS feedback, have been designed and fabricated in a 0.18-μm CMOS technology to investigate their susceptibility to system-level ESD test. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuit provides the lock function to keep the main ESD device in a "latch-on" state. The latch-on ESD device, which is often designed with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. From the experimental results, two kinds of on-chip power-rail ESD clamp circuits with feedback structures are highly sensitive to transient-induced latchup-like failure than others.

Original languageEnglish
Title of host publication2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual
Pages598-599
Number of pages2
DOIs
StatePublished - 25 Sep 2007
Event45th Annual IEEE International Reliability Physics Symposium 2007, IRPS - Phoenix, AZ, United States
Duration: 15 Apr 200719 Apr 2007

Publication series

NameAnnual Proceedings - Reliability Physics (Symposium)
ISSN (Print)0099-9512

Conference

Conference45th Annual IEEE International Reliability Physics Symposium 2007, IRPS
CountryUnited States
CityPhoenix, AZ
Period15/04/0719/04/07

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