Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

Chia Tsen Dai*, Po Yen Chiu, Ming-Dou Ker, Fu Yi Tsai, Yan Hua Peng, Chia Ku Tsai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.

Original languageEnglish
Title of host publication2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012
DOIs
StatePublished - 19 Nov 2012
Event2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012 - Singapore, Singapore
Duration: 2 Jul 20126 Jul 2012

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2012
CountrySingapore
CitySingapore
Period2/07/126/07/12

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