Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology

Shih Hung Chen, Ming-Dou Ker*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

Latchup failure which occurred at only one output pin of a power controller IC product is investigated in this work. The special design requirement of the internal circuits causes the parasitic diode that is inherent between the n-well and p-substrate to be a triggering source of the latchup occurrence in this IC. The parasitic diode of the internal PMOS was easily turned on by an anomalous external signal to trigger the neighbor parasitic Silicon Controlled Rectifier (SCR) path which causes latchup event in the CMOS IC product. Some solutions to overcome this latchup failure have been also proposed in this paper.

Original languageEnglish
Pages (from-to)1042-1049
Number of pages8
JournalMicroelectronics Reliability
Volume46
Issue number7
DOIs
StatePublished - 1 Jul 2006

Fingerprint Dive into the research topics of 'Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology'. Together they form a unique fingerprint.

Cite this