Fabrication technologies for three-dimensional integrated circuits

Rafael Reif, Andy Fan, Kuan-Neng Chen, Shamik Das

Research output: Contribution to journalArticlepeer-review

99 Scopus citations

Abstract

The MIT approach to 3D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: (a) structural integrity of the Cu-Cu bond; (b) Cu-Cu contact electrical characteristics; and (c) process flow efficiency and repeatability. In addition, CAD tools are needed to aid in design and layout of 3DICs. This paper discusses recent results in all these areas.

Original languageEnglish
Article number996687
Pages (from-to)33-37
Number of pages5
JournalProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2002-January
DOIs
StatePublished - 1 Jan 2002

Keywords

  • CMOS technology
  • Computer science
  • Epitaxial growth
  • Fabrication
  • Integrated circuit interconnections
  • Integrated circuit technology
  • Materials science and technology
  • System-on-a-chip
  • Three-dimensional integrated circuits
  • Wafer bonding

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