Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

Po-Jung Sung, Shu-Wei Chang, Kuo-Hsing Kao, Chien-Ting Wu, Chun-Jung Su, Ta-Chun Cho, Fu-Kuo Hsueh, Wen-Hsi Lee, Yao-Jen Lee*, Tien-Sheng Chao

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (T-Si) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.

Original languageEnglish
Pages (from-to)3504-3509
Number of pages6
JournalIeee Transactions On Electron Devices
Volume67
Issue number9
DOIs
StatePublished - 23 Jul 2020

Keywords

  • CMOS
  • complementary field-effect transistor (CFET)
  • junctionless FET (JLFET)
  • nanosheet (NS)
  • poly-Si
  • vertically stacked

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