Fabrication of tri-gated junctionless poly-Si transistors with I-line based lithography

Cheng I. Lin, Ko Hui Lee, Horng-Chih Lin*, Tiao Yuan Huang

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

In this work, we have successfully demonstrated the feasibility of a method, which relies solely on I-line-based lithography, for fabricating sub- 100nm tri-gated junctionless (JL) poly-Si nanowire (NW) transistors. This method employs sidewall spacer etching and photoresist (PR) trimming techniques to shrink the channel length and width, respectively. With this approach, channel length and width down to 90 and 93nm, respectively, are achieved in this work. The fabricated devices exhibit superior device characteristics with low subthreshold swing of 285mV/dec and on/off current ratio larger than 10 7.

Original languageEnglish
Article number04EA01
JournalJapanese Journal of Applied Physics
Volume53
Issue number4 SPEC. ISSUE
DOIs
StatePublished - 1 Jan 2014

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