Fabrication of sub-50-nm gate length n-metal-oxide-semiconductor field effect transistors and their electrical characteristics

Mizuki Ono*, Masanobu Saito, Takashi Yoshitomi, Claudio Fiegna, Tatsuya Ohguro, Hisayo Sasaki Momose, Hiroshi Iwai

*Corresponding author for this work

Research output: Contribution to journalArticle

31 Scopus citations

Abstract

A method of fabricating 40-nm gate-length n-metal-oxide-semiconductor field effect transistors (MOSFETs) is described in detail. The fabrication of MOSFETs with gate lengths of this order poses two major problems: how to fabricate such small-geometry gate electrodes, and how to fabricate the ultrashallow source and drain junctions required. Two special techniques are used to overcome these problems: a resist-thinning process using isotropic oxygen plasma ashing for the fabrication of the gate electrodes, and a process of solid-phase diffusion from phosphorus-doped silicated-glass gate sidewalls for fabrication of the source and drain junctions. The resulting 40-nm gate electrodes and ultrashallow 10-nm junctions have an adequate impurity concentration and have been shown to function successfully. It has been confirmed that these 40-nm gate-length n-MOSFETs have good electrical characteristics at room temperature. Certain details of small-geometry MOSFET electrical characteristics are studied using these devices.

Original languageEnglish
Pages (from-to)1740-1743
Number of pages4
JournalJournal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
Volume13
Issue number4
DOIs
StatePublished - Jul 1995

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