Fabrication and characterization of poly-Si Schottky-barrier thin-film transistors

Poly-Si Schottky-barrier thin-film transistors (SB-TFTs) were fabricated and characterized. In this study, SB-TFTs were first fabricated by using a conventional sidewall spacer to isolate the gate and S/D regions during salicidation. However, it was found that these SB-TFTs depict very poor on/off current ratio (<10 ³ ) as well as severe GIDL (gate-induced drain leakage)-like leakage current. To overcome these shortcomings, a novel SB-TFT structure is also fabricated in this study to improve the device performance. The new device consists of a field-induced-drain region (FID), which is an offset drain region controlled by a metal field-plate lying on top of the passivation oxide. The FID region is sandwiched between the suicided drain and the active channel region. Carrier types and the conductivity of the transistor are controlled by the metal field-plate. Since the metal field plate is formed simultaneously with the regular metal patterning, no additional processing steps are required. Our results show that the new device can significantly improve the on/off current ratio to over 10 ⁶ for both p- and n-channel operations, while effectively eliminating the GIDL-like leakage.