Fabrication and characterization of Pi-gate poly-Si junctionless and inversion mode Fin-FETs for 3-D IC applications

Don Ru Hsieh, Jer Yi Lin, Po Yi Kuo, Tien-Sheng Chao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) Fin-FETs have been successfully fabricated and demonstrated without using costly lithography technique. The PG JL Fin-FETs show excellent electrical performance in terms of low gate overdrive voltage, extremely near-ideal subthreshold swing (S.S.) ∼ 68 mV/dec., steep average subthreshold swing (A.S.S.) ∼ 73 mV/dec., smaller drain induced barrier lowing (DIBL) ∼ 9 mV/V, and higher Ion/Ioff ratio ∼ 1.1 × 108 (VD = 1 V).

Original languageEnglish
Title of host publication2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages110-111
Number of pages2
ISBN (Electronic)9781509007264
DOIs
StatePublished - 27 Sep 2016
Event21st IEEE Silicon Nanoelectronics Workshop, SNW 2016 - Honolulu, United States
Duration: 12 Jun 201613 Jun 2016

Publication series

Name2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

Conference

Conference21st IEEE Silicon Nanoelectronics Workshop, SNW 2016
CountryUnited States
CityHonolulu
Period12/06/1613/06/16

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